Apple PowerBook 520 Technical Information download pdf (Page 51)

CHAPTER 4

Expansion Modules

RAM Expansion Card 37

Table 4-4 shows how the signals are multiplexed during the row and column address

phases. For each type of DRAM device, the ﬁrst and second rows show the actual

address bits that drive each address pin during row addressing and column addressing,

respectively. The third row shows how the device’s address pins are connected to the

signals on the DRAM_ADDR bus.

IMPORTANT

Some types of DRAM devices don’t use all 12 bits in the row or column

address. Address-bit numbers for those unused bits are shown in plain

style; bit numbers for the bits that are used are shown in bold. ▲

Table 4-3 Descriptions of signals on the RAM expansion connector

Signal name Description

CPU_DATA[0–31] Bidirectional 32-bit DRAM data bus.

DRAM_ADDR[0–11] Multiplexed row and column address to the DRAM devices.

(See the section “Address Multiplexing” on page 36 to determine

which bits to use for a given type of DRAM device.)

DRAM_CAS_L[0–3] Column address select signals for the individual bytes in a longword.

The signals are assigned to the bytes as follows:

DRAM_CAS_L[3] selects CPU_DATA[24–31]

DRAM_CAS_L[2] selects CPU_DATA[16–23]

DRAM_CAS_L[1] selects CPU_DATA[8–15]

DRAM_CAS_L[0] selects CPU_DATA[0–7]

DRAM_RAS_L[2–5] Row address select signals for up to four banks of DRAM.

(The ﬁrst two banks, selected by DRAM_RAS_L[1:0], reside

on the CPU and memory module.)

DRAM_WE_L Write enable for the banks of DRAM.

GND Chassis and logic ground.

RESERVED[1–3] Reserved pins; must be left open.

V_5P_MAIN 5.0 ± 5%; 300 mA maximum

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Apple PowerBook 520 Technical Information Page 51