Apple PowerBook 520 Technical Information download pdf (Page 24)

CHAPTER 2

Architecture

10 Processor/Memory Subsystem

The architecture of the PowerBook 520 and 540 computers is partitioned into two

subsystems: the processor/memory subsystem and the input/output subsystem. The

processor/memory subsystem operates at 25 MHz or 33 MHz on the MC68040 bus. The

input/output subsystem operates at 16 MHz on the I/O bus, an MC68030-compatible

bus. An Apple custom IC called the Pratt IC acts as the bridge between the two buses,

translating MC68040 bus cycles into single or multiple MC68030 bus cycles, as needed.

The block diagram shown in Figure 2-1 shows the two subsystems along with other

modules that are attached to them.

Processor/Memory Subsystem 2

The processor/memory subsystem includes the MC68040 microprocessor, main RAM,

and ROM. As Figure 2-1 shows, the processor/memory subsystem is a separate module;

it occupies a secondary logic board mounted above the main logic board. An optional

RAM expansion card attaches to the secondary logic board and becomes part of the

processor/memory subsystem.

The modular design of the PowerBook 520 and 540 computers makes it possible to

upgrade the system by plugging in a whole new processor/memory subsystem. For

example, it will be possible to upgrade to a PowerPC RISC microprocessor when a

low-power version becomes available.

Microprocessor 2

The microprocessor used in the PowerBook 520 and 540 computers is the MC68LC040.

The MC68LC040 does not contain an FPU (floating-point unit). The MC68LC040 does

include a built-in MMU (memory management unit).

The MC68LC040 microprocessor runs at an internal clock rate that is double its external

clock rate. With an external clock rate of 25 MHz, the processor’s internal clock runs at

50 MHz; with an external rate of 33 MHz, the internal clock rate is 66 MHz. Table 1-1 on

page 5 shows the microprocessor type and speed for each of the new models.

RAM 2

The built-in RAM consists of 4 MB of dynamic RAM (DRAM), supplied by eight

1 M by 4-bit ICs on the secondary logic board. The RAM ICs are low-power, self-

refreshing type with an access time of 80 ns.

The RAM array is located in the system memory map between addresses $0000 0000 and

$02FF FFFF, except following a system reset or sleep cycle, when it is overlaid by system

ROM. As in other Macintosh models, the overlay is removed following the first program

access to normal ROM space, making the RAM space accessible.

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Apple PowerBook 520 Technical Information Page 24