Apple Battery Charger User Manual download pdf (Page 18)

18 Maxim Integrated

USB Battery Charger Detectors

MAX14578E/MAX14578AE

Figure 6. Bit Transfer

Figure 7. Acknowledge

Figure 8. Slave Address

Bit Transfer

One data bit is transferred during each clock pulse

(Figure 6). The data on SDA must remain stable while

SCL is high.

Acknowledge

The acknowledge bit is a clocked 9th bit that the

recipient uses to handshake receipt of each byte of

data (Figure 7). Thus, each byte transferred effectively

requires nine bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA during the

acknowledge clock pulse. The SDA line is stable low

during the high period of the clock pulse. When the

master is transmitting to the MAX14578E, it generates

the acknowledge bit because the MAX14578E is the

recipient. When the MAX14578E is transmitting to the

master, the master generates the acknowledge bit

because the master is the recipient.

Slave Address

The MAX14578E has a 7-bit long slave address. The bit

following a 7-bit slave address is the R/W bit, which is

low for a write command and high for a read command.

The slave address is 01011001 for read commands and

01011000 for write commands. See Figure 8.

Bus Reset

The MAX14578E resets the bus with the I

C START

condition for reads. When the R/W bit is set to 1, the

MAX14578E transmits data to the master, thus the mas-

ter is reading from the device.

SDA

SCL

DATA LINE STABLE;

DATA VALID

CHANGE OF DATA

ALLOWED

SCL

SDA

TRANSMITTER

CLOCK PULSE FOR

ACKNOWLEDGE

START

CONDITION

SDA

RECEIVER

1 2 8 9

SDA

ACK

SCL

MSB

LSB

1 R/W

01 00

1 2 ... 13 14 15 16 17 18 19 20 21 22 23

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Apple Battery Charger User Manual Page 18

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